1. Field of the Invention
The present invention relates generally to the field of automated design techniques for electronic circuits, and more particularly to methods and systems for representing very large scale integrated circuit layouts.
2. Description of the Background Art
The physical design of an integrated circuit is generally carried out in terms of the symbolic layout of the topology of the circuit, rather than the actual geometry of the masks and layers that comprise the chip. When creating mask works for integrated circuits, designers typically begin with a circuit schematic 20 consisting of an interconnected network of logic or circuit elements. The designer typically uses a library of mask work patterns or "cells" that correspond to the various circuit elements used in the design. Creating a mask work then consists of transforming the circuit schematic by substituting various cells for the schematic circuit elements in such a way as to provide efficient use of available mask area. The designer can thus work with transistors, wires, and other primitive components, and groups of these components using symbolic representations of these circuit elements. The symbolic layout provides a higher level of abstraction than the mask layout, and is therefore easier for the designer to manipulate. The layout designer is thus allowed to concentrate more on the topological aspects of the circuit design rather than on the spacing requirements of the fabrication technology.
A symbolic cell representation that contains only primitive symbols--i.e. transistors, wires, capacitors and other physical components--is termed a "leaf cell." The connections between cells are made with ports, otherwise known as pins. Leaf cells generally contain rigid geometrical features that define their physical shape, such as definite distances between the ports of the cell.
Many layouts contain a large number of groups of components that are substantially identical. Such a group may be used to define a cell, and the description of the layout may then be simplified by treating each such group as an "instance" of this cell. The cell has its own symbol; for example it may be represented as a rectangle with various ports for connecting wires or for abutment with ports of adjacent cells that are represented similarly. The components of the overall layout then may consist of many cells, and the layout represents their relative placement and interconnection. Describing the layout in terms of cells rather than primitive symbols, further simplifies the designer's task.
Obviously this process of grouping elements and cells may be repeated, so that a symbolic layout can be treated as a hierarchical structure with multiple levels. Each level is a symbolic layout of various cells and primitive components. Each such cell in a level is in turn a symbolic layout of subcells and primitive components, and this layout defines the next lower level of the hierarchy. Since there may be more than one type of cell at any given level, the next lower level may contain several different branches. The cells at the lowest level are the leaf cells since they contain no subcells, but only primitive components. Cells at any other level are "hierarchical cells." The hierarchy can be visualized as an inverted "tree" with branches extending downward, and the lowest level depends on the branch in which it is located. In short, the leaf cells are located at the ends of the branches, and the trunk of the tree represents the symbolic layout of the whole chip, which is often termed the "root cell." This hierarchical description is a natural and concise representation for large designs.
Once the design of the layout is completed, it is tested to verify its logical functioning. Any defective operation is remediated by design changes and reverified. The layout is then compacted, or translated into a mask layout suitable for the actual fabrication of the chip. Compaction maps the symbolic representation of the layout into a physical structure that implements the function of the layout using a specific fabrication technology, while preserving both the topological and geometrical design rules. For example, with semiconductor chips, compaction specifies the configuration of the geometrical structure of the circuit, identifying the precise placement and relationship of the various layers of semiconductors, insulators, substrates and the like. Using the compacted layout, the masks for the circuit are prepared and the circuit fabricated. The fabricated circuit is tested to verify its functional operation. Changes are made to the symbolic layout in order to remediate discrepancies between the intended and actual operation of the circuit, and a new mask work and chip is fabricated. This design and verify process is repeated until the chip operates as intended.
For the symbolic methodology to be effective, it is imperative that the symbolic layout and compaction system handle a variety of design styles. The ability to handle large hierarchical designs is essential. In most hierarchical compaction systems, the connectivity of the circuit elements is implicit in the symbolic layout. Connectivity is extracted from the symbolic layout based on the input topology and is preserved during the compaction process. This is true for both connectivity inside leaf cells as well as the hierarchical connectivity across cells. This implicit representation of connectivity in the symbolic layout causes geometric information to creep into the otherwise topological symbolic layout. Though this may be acceptable for leaf cells, it has serious draw backs in designing hierarchical layouts, and significantly reduces the effectiveness of the symbolic methodology. When leaf cells are designed for use in hierarchical layouts, the position of pins or ports in these cells, that connect to other cells is constrained by the abutment requirements. This is because when cells are placed in a particular configuration during the symbolic design of hierarchical layouts, s the connectivity across cells is implicit by overlapping of symbols. Hence the pin or port positions for the cells must be decided before the actual symbolic layout of leaf cells which can lead to sub-optimum designs.
FIG. 1 shows a hierarchical layout containing two instances of two leaf cells A and B, with abutting pins 11. Each leaf cell contains geometrical information specifying its size along the x and y axis, and the spacing requirements d(1) and d(2) between the pins 11. Due to the abutting requirements between the pins 11 on the common boundary 13, the relative position of these pins 11 in the two cells should be the same. Determining these pin positions in the overall layout, consistent with numerous other leaf and hierarchical cells, with conventional symbolic representation and compaction is difficult and often requires multiple iterations. Moreover, the placement of the pin positions in the symbolic layout constrains the design of each leaf cell, reducing the flexibility and reusability of the leaf cell in other circuit implementations. Another significant disadvantage with conventional approaches is that engineering change orders (ECO's) become very difficult to incorporate into an existing layout. Once the hierarchy has been built, it is very tedious to make any changes to one of the leaf cells which would require its size or the position of one of the pins or ports to change. The change in the pin position in one of the leaf cells would cause a rippling effect in other cells and in some cases the whole hierarchy may have to be redesigned, at a significant cost.
It is desirable therefore to provide a method of symbolically representing a circuit layout that separates the layout design process into topological and geometrical design stages. Such a bifurcated design process has two distinct advantages. First, it offers process independence. The same topological or symbolic design can be targeted to many different processes since the specific geometric constraints for a given fabrication technology are not incorporated into the symbolic layout. Process independence is important for fabless semiconductor companies, as the binding to a specific technology can be delayed to later in the design cycle. The second advantage is that it allows higher level tools such as layout synthesis and layout generators to compile into the more abstract intermediate representation without having to be concerned with the exact design rules. Design space exploration is facilitated since different topologies can be generated more easily.
In order to provide for a distinct topological design stage, it is desirable to provide a method for representing the topological structure and their connectivity relations of a circuit layout without deriving the structure from the geometrical features of the cells. What is further needed is a method of representation that is devoid of geometrical information at the hierarchical cell level, and hence produces a true symbolic format, whereby intercell connectivity requirements are explicitly captured by the connections between cell instances in the hierarchy, leaving considerable freedom for the design of the leaf cells. Such a method should provide all the necessary information for producing a compacted hierarchical layout without specifying the geometrical features of the layout.